? semiconductor components industries, llc, 2015 august, 2015 ? rev. 0 1 publication order number: CSPEMI204/d CSPEMI204 emi filter with esd protection product description the CSPEMI204 is an l?r?c emi filter array with esd protection that integrates two pi?filters (c?l?r?c) to suppress emi/rfi noise. CSPEMI204 includes esd protection diodes on all input/output pins, and provides a very high level of protection for sensitive electronic components against possible electrostatic discharge (esd). the esd diodes connected to the filter ports safely dissipate esd strikes of 30 kv, which is beyond the maximum requirement of the iec61000?4?2 international standard. features ? two channels of emi filtering ? 30 kv esd protection (iec 61000?4?2, contact discharge) ? 30 kv esd protection (iec 61000?4?2, air discharge) ? greater than 45 db of attenuation at 900 mhz ? these devices are pb?free, halogen free/bfr free and are rohs compliant applications ? mobile phones maximum ratings (t a = 25 c) rating symbol value unit esd discharge iec61000?4?2 contact discharge air discharge v pp 30 30 kv rms current per line i line 350 ma operating temperature range t j ?40 to +125 c storage temperature range t stg ?55 to +150 c lead solder temperature (10 second duration) t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. marking diagram device package shipping ? ordering information www. onsemi.com CSPEMI204fctag wlcsp5 (pb?free) 5000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. wlcsp5 fc suffix case 567ma block diagram at = specific device code m = date code atm a1 c1 gnd b1 a3 c3 gnd b1 filter#1 filter#2
CSPEMI204 www. onsemi.com 2 table 1. pin descriptions pin name description a1 filter #1 filter #1 input/output c1 filter #1 filter #1 input/output a3 filter #2 filter #2 input/output c3 filter #2 filter #2 input/output b2 gnd device ground package/pinout diagrams top view (bumps down view) a bottom view (bumps up view) orientation marking wlcsp5 package c a3 c3 1 2 3 + at a1 c1 b2 b + table 2. electrical operating characteristics (t a = 25 c unless otherwise noted) symbol parameter test conditions min typ max unit v rwm working voltage 3.0 v v br breakdown voltage i t = 1 ma; (note 4) 6.0 v i leak channel leakage current v in = 3.0 v , gnd = 0 v 400 na r ch channel resistance (pins a1 ? a3, c1 ? c3) 3.0 c t line capacitance v r = 0 v, f = 1 mhz 185 250 315 pf f 3db cut - off frequency 450 source and 10 k load termination 2.0 mhz f 3db cut - off frequency 50 termination 25 mhz f atten stop band attenuation @ 700 mhz @ 900 mhz 40 47 db v esd in - system esd withstand voltage a) contact discharge per iec 61000 - 4 - 2 standard, level 4 (external pins) b) contact discharge per iec 61000 - 4 - 2 standard, level 1 (internal pins) (notes 1 and 2) 30 30 kv v cl tlp clamping voltage forward i pp = 8 a forward i pp = 16 a forward i pp = 8 a forward i pp = 16 a 9.8 11.5 ?9.7 ?11.7 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. standard iec61000?4?2 with c discharge = 150 pf , r discharge = 330, gnd grounded. 2. these measurements performed with no external capacitor . 3. tvs devices are normally sele cted according to the working peak reverse voltage (v rwm ), which should be equal to or greater than the dc or continuous peak operating voltage level. 4. v br is measured at pulse test current i t .
CSPEMI204 www. onsemi.com 3 performance information typical filter performance figure 1. typical insertion loss (50 termination) 1.e+07 1.e+08 1.e+09 1.e+10 ?60 ?50 ?40 ?30 ?20 ?10 0 frequency (hz) s21 (db) figure 2. typical thd+n at 1.8 v pp 20 200 2000 20000 ?120 ?115 ?110 ?105 ?100 ?95 ?90 frequency (hz) thd+n (db) 1.e+05 1.e+06 figure 3. typical insertion loss (450 source and 10 k load termination) 1.e+07 1.e+08 1.e+09 1.e+ 11 ?60 ?50 ?40 ?30 ?20 ?10 0 frequency (hz) s21 (db) 1.e+05 1.e+06 1.e+10 ?100 ?90 ?80 ?70 ?85 ?80
CSPEMI204 www. onsemi.com 4 iec 61000?4?2 spec. level test volt- age (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000?4?2 w aveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 4. iec61000?4?2 spec figure 5. diagram of esd clamping voltage test setup 50 50 cable tvs oscilloscope esd gun the following is taken from application note and8308/d ? interpretation of datasheet parameters for esd devices. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000?4?2 waveform. since the iec61000?4?2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d.
CSPEMI204 www. onsemi.com 5 figure 6. positive tlp i?v curve (preliminary) figure 7. negative tlp i?v curve (preliminary) tlp current (a) v c , voltage (v) 25 014 12 246 10 8 tlp current (a) v c , voltage (v) ?25 0 ?14 ?12 ?10 ?2 ?4 ?6 ?8 note: tlp parameter: z 0 = 50 , t p = 100 ns, t r = 300 ps, averaging window: t 1 = 30 ns to t 2 = 60 ns. v iec is the equivalent voltage stress level calculated at the secondary peak of the iec 61000?4?2 waveform at t = 30 ns with 2 a/kv. see tlp description below for more information. 20 15 10 5 0 ?20 ?15 ?10 ?5 0 transmission line pulse (tlp) measurement transmission line pulse (tlp) provides current versus voltage (i?v) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. a simplified schematic of a typical tlp system is shown in figure 8. tlp i?v curves of esd protection devices accurately demonstrate the product?s esd capability because the 10s of amps current levels and under 100 ns time scale match those of an esd event. this is illustrated in figure 9 where an 8 kv iec 61000?4?2 current waveform is compared with tlp current pulses at 8 a and 16 a. a tlp i?v curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. figure 8. simplified schematic of a typical tlp system dut l s oscilloscope attenuator 10 m v c v m i m 50 coax cable 50 coax cable figure 9. comparison between 8 kv iec 61000?4?2 and 8 a and 16 a tlp waveforms
CSPEMI204 www. onsemi.com 6 package dimensions wlcsp5, 1.26x0.89 case 567ma issue o seating plane 0.10 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 4. dimension b is measured at the maximum ball diameter parallel to datum c. 2x dim a min max ??? millimeters a1 d 1.26 bsc e b 0.235 0.295 e 0.50 bsc 0.50 e d a b pin a1 reference e a 0.10 b c 0.05 c 0.05 c 5x b 123 c b a 0.10 c a a1 a2 c 0.18 0.22 0.89 bsc e1 0.435 bsc 0.50 0.27 5x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.87 0.10 c 2x top view side view bottom view note 3 e1 a2 0.255 ref recommended a1 package outline e/2 pitch pitch on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 CSPEMI204/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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